1. Field of the Invention
The present invention relates generally to methods for programming semiconductor memory cells, and more particularly, to a programming method for controlling memory threshold voltage distributions for one or more double-sided semiconductor memory cells.
2. Description of the Related Art
A semiconductor memory cell, or a memory cell, such as a nitride read only memory (NROM) cell, is typically programmed by applying a programming pulse thereto, thus causing charges to become trapped in a retention layer of the memory cell. The trapped charges in the retention layer of a memory cell induce the increase of the threshold voltage for the memory cell.
In order to verify whether the increased threshold voltage of the programmed memory cell has reached its target programming voltage, a verifying pulse, following the programming pulse, is applied to the programmed memory cell. If the verifying pulse reveals that the programmed memory cell has not yet reached the target programming voltage, an additional programming pulse is applied, followed by a subsequent verifying pulse. Typically, during the programming process, the programming pulse increases in voltage levels, commencing at a relatively low voltage level and terminating at a higher voltage level. The programming and the verifying will continue until the target programming voltage has been reached.
For a multiple-leveled double-sided memory cell, different target programming voltages might exist for each side of the memory cell. The programming method for a double-sided memory cell typically involves programming and verifying one side of the memory cell until its threshold voltage reaches the target programming voltage for this side, then programming and verifying the other side of the memory cell until its threshold voltage reaches its target programming voltage.
FIG. 1 is a flow chart 100 illustrating a conventional programming method for a multiple-leveled double-sided memory cell. The programming operation commences with selecting the right side to be programmed (step 110). In step 120, the selected side is applied with a programming pulse. A verifying pulse for the selected side is followed in step 130. The verification result is queried in step 140, determining whether the threshold voltage of the selected side reaches its target programming voltage. If the target programming voltage for the selected side is not reached, the selected side does not pass the verification. The programming pulse will be adjusted, usually to a higher voltage level, in step 170, the programming (step 120) and the verifying (step 130) will be performed again for the selected side. If the selected side passes the verification, i.e., its threshold voltage reaches its target programming voltage, both sides of the memory cell will be checked to see whether they have reached their target programming voltages in step 150. If the other side needs to be programmed, the left side is selected and the program condition is reset in step 160. The programming and the verifying processes will start for the newly selected side (left side).
The conventional programming method for multiple-leveled double-sided memory cells mainly has the following drawbacks. First of all, due to the second bit effect, the threshold voltages of one side of the memory cell will be affected by the charge stored at the other side of the memory cell. Secondly, the array effect will affect the threshold voltage distributions for a memory cell in a memory array, i.e., the threshold voltage of a selected memory cell will be affected by the leakage current to neighboring memory cells that share the same word line with the selected memory cell, thus resulting in difficulties to achieve narrow threshold voltage distributions. Wide threshold voltage distributions for a memory array will reduce the read margin window for memory array between a programming state and an erased state.
FIG. 2 shows three diagrams illustrating the threshold voltage Vt distributions of a 9-cell NROM array that are programmed by a conventional programming method. Each NROM cell of the NROM array is capable of double-sided operations. The target programming voltage PV for both sides of the NROM cells in the NROM array is 4V. The programming for the NROM array includes three steps: 201, 202, and 203.
In step 201, no charges are stored at both the right sides and the left sides of the NROM cells in the NROM array. The threshold voltage distributions 210 and 220 are the threshold voltage distributions for the left sides and the right sides of the NROM cells in the NROM array when no charges are stored at both sides.
In step 202, the right sides of the NROM cells in the NROM array are programmed to achieve the target programming voltage 4V. The threshold voltage distribution 240 is the threshold voltage distribution for the right sides of the NROM array after the right sides of the NROM array are programmed. As shown, although the left sides of the NROM array are not programmed in step 202, the second bit effect causes the threshold voltage distribution 210 for the left sides of the NROM array to shift to a higher threshold voltage region, forming the threshold voltage distribution 210′. The low bond threshold voltage shift between the threshold voltage distributions 210 and 210′ is 231 mV, while the high bond threshold voltage shift between the threshold voltage distributions 210 and 210′ is 152 mV.
In step 203, the left sides of the NROM cells in the NROM array are programmed until the target programming voltage 4V is reached. The threshold voltage distribution 230 is the threshold voltage distribution of the left sides of the NROM array after the left sides of the NROM array are programmed. As shown, due to the second bit effect, the threshold voltage distribution 240 for the right sides of the NROM array has shifted to a higher threshold voltage region, forming the threshold voltage distribution 240′. The low bond threshold voltage shift between the threshold voltage distributions 240 and 240′ is 168 mV, while the high bond threshold voltage shift between the threshold voltage distributions 240 and 240′ is 207 mV. In addition, the width of threshold voltage distribution 240 is increased from 86 mV to 125 mV in the threshold voltage distribution 240′. The deviations and the increased widths of the threshold voltage distributions make the threshold voltage distributions of the NROM cells difficult to control.
In view of the foregoing, there is a need for a programming method for one or more double-sided memory cells that can reduce the impacts of the second bit effect and the array effect to the threshold voltage distributions of the memory cells.